Abstract:
Today's computer hardware are highly optimized general purpose architectures 
but unavoidable inefficient in terms of special purpose scenarios. The grade 
of efficiency usual ly has to face a business economical consideration to 
choose between special versus general purpose hardware. The emerging technology 
of programmable logic devices enables a new kind of architecture for massively 
parallel systems based on programmable logic devices. For such systems the 
traditional way of chip configuration is not useful anymore. This paper 
presents a concept for configuring massively paral lel reconfigurable 
architectures. Furthermore a proof of concept is given by applying the 
configuration schemeto an reconfigurable architecture consisting of 120 
chips.

BibTeX:
@InProceedings{I-KPPPS06,
  author =	 {S. Kumar and C. Paar and J. Pelzl and G. Pfeiffer
                  and M. Schimmler},
  title =	 "{A Configuration Concept for a Massively Parallel FPGA Architecture}",
  booktitle =	 {International Conference on Computer Design --- CDES'06, Las Vegas, USA},
  month =	 {June 26-29},
  year =	 {2006}
}